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第三十五讲 Ultra-Energy-Efficient Machine Learning Hardware: Microwatt Biomedical Processor and In-Memory

日期: 2018-08-24
撰稿人:

第三十五讲 Ultra-Energy-Efficient Machine Learning Hardware: Microwatt Biomedical Processor and In-Memory

讲座详情

演讲题目Ultra-Energy-Efficient Machine Learning Hardware: Microwatt Biomedical Processor and In-Memory Computing Designs

演讲时间:2018年8月28日上午10:00

演讲地点:荷清大厦A座一层水木会议室

主讲人: Jae-sun Seo  

二、主讲人介绍

Jae-sun Seo received his Ph.D. degree from University of Michigan in 2010. From 2010 to 2013, he was with IBM T. J. Watson Research Center, where he worked on energy-efficient circuits for microprocessors and cognitive computing chip design for the DARPA SyNAPSE project. In January 2014, he joined Arizona State University as an assistant professor in the School of ECEE. His research interests include efficient hardware design for deep learning and neuromorphic computing, as well as integrated power management. During the summer of 2015, he was a visiting faculty at Intel Circuits Research Lab. He was a recipient of IBM OutstandingTechnical Achievement Award in 2012 and NSF CAREER Award in 2017. 

三、演讲内容

In recent years, deep learning algorithms have been widespread across many practical applications. Algorithms trained by offline back propagation using pre-defined datasets show impressive performance, but state-of-the-art algorithms are compute-/memory-intensive, making it difficult to perform low-power real-time classification with low energy consumption on embedded hardware platforms.

This is especially true for wearable devices that exhibit very stringent power and area constraints. Targeting a smart security engine on wearable devices, I will first present a 1µW ECG ASIC processor with highly compressed neural networks, which demonstrates ECG-based authentication on a >600-subject database.

Next, I will discuss our recent works on “in-memory computing” (analog computation along bitline with all rows asserted) for deep learning systems, which is apromising technique to achieve large energy gains over all-digital ASIC. We have designed new bitcells and macros for in-memory computing based on both SRAM (65nm) and RRAM (monolithic integration with 90nm CMOS) and fabricated prototype chips. Compared to row-by-row sequential designs, our SRAM and RRAM in-memory computing prototype chips show >30X energy improvement on MAC and convolution operations, while maintaining >85% accuracy on CIFAR-10 dataset.

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